Serial Communication

• Data communication is a general technique for two endpoints to communicate with each other.
• Data is sent from one endpoint and received by the other endpoint and vice versa.
• Serial communication describes the scenario where the data bits are transmitted sequentially (one bit at a time).
• Parallel communication describes the scenario where multiple bits are transmitted simultaneously.

There are many forms of serial communication. For example:

• USB (universal serial bus)
• Firewire
• Bluetooth
• IR
• Ethernet
• WiFi
• RS-232 (Recommended Standard 232) (Although newer versions exist, revision C was released in 1969)

• RS-232 voltages:
  • A voltage between 3 and 15V is deemed to be logic 0.
  • A voltage between -3 and -15V is deemed to be logic 1.
• The actual voltage depends on the power supply (commonly +-5 or +-12V)
• The big voltage swing (required by the RS-232 standard) makes it less desirable for low-power hardware. As a result, modern laptops and handheld devices use low-power alternatives like USB or firewire.

The ATmega32 provides the following serial communication options:

• The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) subsystem (on PortD).
• The synchronous peripheral interface (SPI) (on PortB)
• A two-wire interface (TWI) (on PortC).

The USART is a standardized device that can:

• Transmit a binary number as a square wave to a receiver.
• Receive a square wave and convert the information into a binary number.
• Transmit and receive at the same time (full duplex).
• Use interrupts to signal that a transmit and/or receive is complete.

• In synchronous mode, the two endpoints must keep their clock signals synchronized.
• A master clock signal is transmitted to the receiver to coordinate data bit sampling through time.
• Even when no data is being sent, the two devices continuously exchange “sync” characters.

• In asynchronous mode, the two endpoints each manage their own clock.
• Nothing is transmitted when there is nothing to send (no master clock is transmitted).
• A “handshake” must be established whenever data needs to be transmitted.
• The USART has built-in hardware to synchronize to an incoming signal.

We'll just look at the asynchronous mode.

We will focus on the USART subsystem.

• Hardwired to PORTD
  • RXD pin is used to receive serial data (PD0)
  • TXD pin is used to transmit serial data (PD1)
  • The USART overrides functionality for PD0 and PD1 when enabled
• The ATmega32 ports are driven by Transistor-Transistor Logic (TTL)
  • A voltage between 0 and 2V is deemed to be logic 0.
  • A voltage between 3 and 5V is deemed to be logic 1.
• The SunRom board includes an RS-232 converter chip
  • The RS-232 IC converts from the TTL logic levels to those required by the RS-232 standard.

Serial transmission of one data frame:

• St – start bit, always low, 1 bit required
• (n) – data bits (0 - 8), 5 to 9 bits required
  • 0 is the least significant bit
  • 1 is the next least significant bit, etc…
• P – Parity bit, (configurable for even or odd parity) optional
• Sp1/Sp2 – stop bits, always high, second stop bit is optional
• IDLE – Indicates no transfers on RxD or TxD (always high)

• The parity bit is an error checking mechanism used to detect data corruption.
• The parity bit is calculated by applying an exclusive-or operation to all of the data bits.
• Using even parity, the parity bit is calculated as P_even = d_n-1 XOR … XOR d₂ XOR d₁ XOR d₀ XOR 0.
• Using odd parity, the parity bit is calculated as P_even = d_n-1 XOR … XOR d₂ XOR d₁ XOR d₀ XOR 1.
• The transmitter calculates the correct value for the parity bit prior to sending the data frame and includes it in the data frame.
• The receiver calculates the correct value for the parity bit based on the data bits and compares it to the value of the parity bit sent.
• If the calculated and received parity bit values differ, an error is indicated.
• The parity bit is a reliable indicator of an error as long as no more than one bit in the data frame is corrupted.
• The parity bit cannot be used to correct the error in the data frame, it only detects an error.

• The speed of serial transmission is typically described in bits-per-second.
• This is called the baud rate.
• Note that the overhead (start bit, stop bit(s), parity bit) are counted in the bits per second, so 2400 baud is not the same as 300 characters per second.
• The USART can be configured to operate between 2400 and 1M

• UCSRA: USART Control and Status Register A
  • Mainly a status register indicating when events have completed
  • Indicates when subsystem has completed tasks
  • Useful when polling
  • RXC: USART Receive Complete
  • TXC: USART Transmit Complete
  • UDRE: USART Data Register Empty
  • FE: Frame Error – first stop bit was zero (should always be one)
  • DOR: Data OverRun – receiving another character before the buffered character is read
  • PE: Parity Error
  • U2X: Double the USART Transmission Speed
  • MPCM: Multi-Processor Communication Mode – we won't use
• UCSRB: USART Control and Status Register B
  • Mainly a control register
  • Used to enable interrupts
  • RXCIE: RX Complete Interrupt Enable
  • TXCIE: TX Complete Interrupt Enable
  • UDRIE: USART Data Register Empty Interrupt Enable
  • RXEN: Receive Enable
  • TXEN: Transmitter Enable
  • UCSZ2: Character size (used in conjunction with UCSZ1:0 in UCSRC
  • RXB8: Receive Data Bit 8 (9^th data bit)
  • TXB8: Transmit Data Bit 8 (9^th data bit)
• UCSRC: USART Control and Status Register C
  • Mainly a control register
  • Configures the communication model:
    • Synchronous/Asynchronous
    • Parity bit control (odd/even/none)
    • Data size (along with one bit from UCSRB)
  • URSEL: Register Select (1 for UCSRC, 0 for UBRRH)
  • UMSEL: USART Mode Select (0 for Asynchronous, 1 for Synchronous)
  • UPM1:0 Parity mode
    • 00: None
    • 10: Even Parity
    • 11: Odd Parity
  • USBS: Stop Bit Select (0 for 1-bit, 1 for 2-bit)
  • UCSZ1:0: Character Size (UCSZ2:0 = 011 for 8 bit)
  • UCPOL: Clock Polarity
    • Used in synchronous mode only (use 0 when in asynchronous mode)
    • 0 – transmit on rising XCK edge, receive on failing XCK edge
    • 1 – transmit on failing XCK edge, receive on rising XCK edge
• UDR: USART I/O Data Register
  • The Transmit Data Buffer Register and Receive Data Buffer Register share this register
  • Writing to UDR sends data to the Transmit Data Buffer Register (TXB), when empty, to be sent out on TXD and initiates a transmission (data written to UDR and then copied to TXD)
    • If TXB still contains data that is being transmitted, the data written to the UDR stays there until the TXB is available
  • Reading from UDR returns the contents of the Receive Data Buffer Register (RXB) received on RXD (contents of RXB is copied to UDR and then returned)
    • When receiving, the bits are accumulated in the RXB buffer
    • Once the tranmission is complete (the stop bit has been received), the contents of RXB are written to UDR
    • Another transmission can begin (filling bits into RXB)
• UBRRH and UBRRL: USART Baud Rate Registers
  • UBRRH shares the same memory address as UCSRC
    • MSB (URSEL) in UBRRH/UCSRC determines which register is of interest
    • URSEL must be zero when writing to UBRRH
    • URSEL is zero when reading from UBRRH
  • USART Baud Rate is set via the following equation:
    • is the system clock frequency
    • is the desired baud rate
    • Therefore, for 9,600 baud, we would need UBRR = 103 for a 16MHz system clock
  • Write 0 to upper nibble of UBRRH
  • Lower nibble of UBRRH contains UBRR[11:8]
  • UBRRL contains UBRR[7:0]

1. Initialize the control registers for the desired baud rate and frame format (stop bit(s), parity, data size)
2. Enable Transmit (TXEN) and Receive (RXEN) via UCSRB
3. Disable all USART interrupts via UCSRB to avoid conflicts with ATmon

Polled mode can be used to monitor:

• The receive complete, RXC, status flag to determine if new data has arrived
  • Must keep polling RXC to avoid dropping received characters
• The UDR empty, UDRE, status flag to determine if a transmission is complete
  • Note: You must ensure that UDRE is set before writing to UDR
  • Keep in mind that 9600 baud is a lot slower than the 16MHz clock